work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_flwsp.h

diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
index 2d2dd5ccc2980423b20d5349c51f80a7945ee239..26a47216b88cac42afca46367ba051a72758e455 100644 (file)
--- a/riscv/insns/c_flwsp.h
+++ b/riscv/insns/c_flwsp.h
@@ -3,7 +3,7 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   WRITE_FRD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
-} else {
+} else { // c.ldsp
   require(insn.rvc_rd() != 0);
   WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
 }