work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_fsw.h

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 4089e3d42e7ef785adbdf8e17d9c67fc0fc8df94..8923fef38fb1a5f88780cb1d893736809126b16a 100644 (file)
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
-} else {
+} else { // c.sd
   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
 }