work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_jal.h

diff --git a/riscv/insns/c_jal.h b/riscv/insns/c_jal.h
index b63967c783a86357b18b3f207c871c788bc801b9..068c441ee2c3f02f36c94d0b49af63371c89f036 100644 (file)
--- a/riscv/insns/c_jal.h
+++ b/riscv/insns/c_jal.h
@@ -1,4 +1,8 @@
 require_extension('C');
-reg_t tmp = npc;
-set_pc(pc + insn.rvc_j_imm());
-WRITE_REG(X_RA, tmp);
+if (xlen == 32) {
+  reg_t tmp = npc;
+  set_pc(pc + insn.rvc_j_imm());
+  WRITE_REG(X_RA, tmp);
+} else {
+  WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));
+}