Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_li.h

diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
index 52e99c96005b996b87bce4b9552cb936bca69c6a..844686dd21d9a595a8c095463eb98fdc6b778a53 100644 (file)
--- a/riscv/insns/c_li.h
+++ b/riscv/insns/c_li.h
@@ -1,7 +1,3 @@
 require_extension('C');
 require(insn.rvc_rd() != 0);
-if (insn.rvc_imm() == 0) { // c.jr
-  set_pc(RVC_RS1 & ~reg_t(1));
-} else {
-  WRITE_RD(insn.rvc_imm());
-}
+WRITE_RD(insn.rvc_imm());