more work towards RVC 1.8

[riscv-isa-sim.git] / riscv / insns / c_lui.h

diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index e5060a37892ab6fbb184de2819d25d9b48fb2a98..130aaed8f4c93bc9cc23b12909bb1a7db5e31d60 100644 (file)
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,3 +1,8 @@
 require_extension('C');
-require(insn.rvc_rd() != 0);
-WRITE_RD(insn.rvc_imm() << 12);
+if (insn.rvc_rd() == 2) { // c.addi16sp
+  require(insn.rvc_addi16sp_imm() != 0);
+  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
+} else {
+  require(insn.rvc_rd() != 0);
+  WRITE_RD(insn.rvc_imm() << 12);
+}