New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_lw.h

diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index f2fc2991d32a0fe5925cf048c8a6bf9fb0892605..ef49dd90904f1608b9a5320cb8ccd17228020ee1 100644 (file)
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
 require_extension('C');
-WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
+WRITE_RVC_RS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));