New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_slli.h

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index de3683b9e4a547d77b11f0ce270dffa87c01dca5..6bbefb18ac312e7d0bd0ec3e828f81d2cf493289 100644 (file)
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,4 +1,3 @@
 require_extension('C');
-if (insn.rvc_imm() >= xlen)
-  throw trap_illegal_instruction();
-WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));
+require(insn.rvc_imm() < xlen);
+WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_imm()));