New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_swsp.h

diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h
index 6f3fef0dcdf15855f30a3a3e4a35ee5c6d4e7182..b8995ab05fd0596626e8c6a5d1770fc45cbd67d9 100644 (file)
--- a/riscv/insns/c_swsp.h
+++ b/riscv/insns/c_swsp.h
@@ -1,2 +1,2 @@
 require_extension('C');
-MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);
+MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2);