Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrc.h

diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h
index eae91fe661cdab82ec3eac33948fc35f3e4ab41a..0472d80efd5164b885d99d94f7a58d8359a26037 100644 (file)
--- a/riscv/insns/csrrc.h
+++ b/riscv/insns/csrrc.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old & ~RS1);
 }
 WRITE_RD(sext_xlen(old));
+serialize();