Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrci.h

diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index 986d6013aa858bfad336e5c5f71dbd586b26e347..4d83cc0617edd871ebb9ad823d86a4663c310ce9 100644 (file)
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old & ~(reg_t)insn.rs1());
 }
 WRITE_RD(sext_xlen(old));
+serialize();