Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrci.h

diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index 993f2d832ba8f6c0b2f42ea0698289ed2d764187..4d83cc0617edd871ebb9ad823d86a4663c310ce9 100644 (file)
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -1,4 +1,8 @@
-int csr = validate_csr(insn.csr(), true);
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
 reg_t old = p->get_csr(csr);
-p->set_csr(csr, old & ~(reg_t)insn.rs1());
+if (write) {
+  p->set_csr(csr, old & ~(reg_t)insn.rs1());
+}
 WRITE_RD(sext_xlen(old));
+serialize();