Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrci.h

diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index d671f3b0b7ed10fd8c28df1cf10c0f9c0d51c033..4d83cc0617edd871ebb9ad823d86a4663c310ce9 100644 (file)
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -1,2 +1,8 @@
-int csr = validate_csr(insn.i_imm(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) & ~(reg_t)insn.rs1()));
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
+reg_t old = p->get_csr(csr);
+if (write) {
+  p->set_csr(csr, old & ~(reg_t)insn.rs1());
+}
+WRITE_RD(sext_xlen(old));
+serialize();