Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrs.h

diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index 72b49bbe9d7d645e1c15f596c6fc0b79ff9531f1..4e8bde96379935755ef87b32903e5aadd81a5227 100644 (file)
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -1,4 +1,8 @@
-int csr = validate_csr(insn.csr(), insn.rs1() != 0);
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
 reg_t old = p->get_csr(csr);
-p->set_csr(csr, old | RS1);
+if (write) {
+  p->set_csr(csr, old | RS1);
+}
 WRITE_RD(sext_xlen(old));
+serialize();