Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrs.h

diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index ba315d41fa121c5f514ee5d83dba226e977de590..4e8bde96379935755ef87b32903e5aadd81a5227 100644 (file)
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -1,2 +1,8 @@
-int csr = validate_csr(insn.csr(), insn.rs1() != 0);
-WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | RS1)));
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
+reg_t old = p->get_csr(csr);
+if (write) {
+  p->set_csr(csr, old | RS1);
+}
+WRITE_RD(sext_xlen(old));
+serialize();