Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrsi.h

diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h
index 827d2d081c7268243bf77850de183fbe0ca424b5..b673725b54d1cbc8eb0a4e27e4af7d6563eb45b6 100644 (file)
--- a/riscv/insns/csrrsi.h
+++ b/riscv/insns/csrrsi.h
@@ -1,2 +1,8 @@
-int csr = validate_csr(insn.csr(), true);
-WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1())));
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
+reg_t old = p->get_csr(csr);
+if (write) {
+  p->set_csr(csr, old | insn.rs1());
+}
+WRITE_RD(sext_xlen(old));
+serialize();