projects
/
riscv-isa-sim.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
| inline |
side by side
Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
csrrsi.h
diff --git
a/riscv/insns/csrrsi.h
b/riscv/insns/csrrsi.h
index aa44dcca8543ac374400450e4cc4326fc24652bc..b673725b54d1cbc8eb0a4e27e4af7d6563eb45b6 100644
(file)
--- a/
riscv/insns/csrrsi.h
+++ b/
riscv/insns/csrrsi.h
@@
-5,3
+5,4
@@
if (write) {
p->set_csr(csr, old | insn.rs1());
}
WRITE_RD(sext_xlen(old));
+serialize();