Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrw.h

diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 4b16773d6cbc02dce6c20756412b322f4c983157..e45420b570bc52c8bd53e2aaaf893eb6db3b3607 100644 (file)
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,2 +1,5 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, RS1));
+reg_t old = p->get_csr(csr);
+p->set_csr(csr, RS1);
+WRITE_RD(sext_xlen(old));
+serialize();