Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrw.h

diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 9f2324ff6f3fc859ffb3ece63495af9e55ed914c..e45420b570bc52c8bd53e2aaaf893eb6db3b3607 100644 (file)
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -2,3 +2,4 @@ int csr = validate_csr(insn.csr(), true);
 reg_t old = p->get_csr(csr);
 p->set_csr(csr, RS1);
 WRITE_RD(sext_xlen(old));
+serialize();