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Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
csrrw.h
diff --git
a/riscv/insns/csrrw.h
b/riscv/insns/csrrw.h
index b98166584b68decc869a9f7ed4ffbc624324b29a..e45420b570bc52c8bd53e2aaaf893eb6db3b3607 100644
(file)
--- a/
riscv/insns/csrrw.h
+++ b/
riscv/insns/csrrw.h
@@
-1,4
+1,5
@@
int csr = validate_csr(insn.csr(), true);
-reg_t old = p->get_
pc
r(csr);
-p->set_
pc
r(csr, RS1);
+reg_t old = p->get_
cs
r(csr);
+p->set_
cs
r(csr, RS1);
WRITE_RD(sext_xlen(old));
+serialize();