Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrwi.h

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index 840150e01ae18ca953708134db14131559661a8d..decadf412141076aec92ec58c4a9101e26456c06 100644 (file)
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,5 @@
-int csr = validate_csr(insn.i_imm(), true);
-WRITE_RD(p->set_pcr(csr, insn.rs1()));
+int csr = validate_csr(insn.csr(), true);
+reg_t old = p->get_csr(csr);
+p->set_csr(csr, insn.rs1());
+WRITE_RD(sext_xlen(old));
+serialize();