Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrwi.h

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index b8ec5f5f90d6c7797908c1fe28ea9e83ed478edf..decadf412141076aec92ec58c4a9101e26456c06 100644 (file)
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,5 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(sext_xprlen(p->set_pcr(csr, insn.rs1())));
+reg_t old = p->get_csr(csr);
+p->set_csr(csr, insn.rs1());
+WRITE_RD(sext_xlen(old));
+serialize();