Include math.h for NAN (#137)

[riscv-isa-sim.git] / riscv / interactive.cc

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 748f454e0ae682c80967289dfa95c05e427e2328..dbcd22455d5fe6fdb75388946df176d7227ca6df 100644 (file)
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -17,13 +17,16 @@
 #include <string>
 #include <vector>
 #include <algorithm>
+#include <math.h>
+
+DECLARE_TRAP(-1, interactive)
 
 processor_t *sim_t::get_core(const std::string& i)
 {
   char *ptr;
   unsigned long p = strtoul(i.c_str(), &ptr, 10);
-  if (*ptr || p >= num_cores())
-    throw trap_illegal_instruction();
+  if (*ptr || p >= procs.size())
+    throw trap_interactive();
   return get_core(p);
 }
 
@@ -64,6 +67,7 @@ void sim_t::interactive()
   funcs["r"] = funcs["run"];
   funcs["rs"] = &sim_t::interactive_run_silent;
   funcs["reg"] = &sim_t::interactive_reg;
+  funcs["freg"] = &sim_t::interactive_freg;
   funcs["fregs"] = &sim_t::interactive_fregs;
   funcs["fregd"] = &sim_t::interactive_fregd;
   funcs["pc"] = &sim_t::interactive_pc;
@@ -161,7 +165,7 @@ void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::stri
 reg_t sim_t::get_pc(const std::vector<std::string>& args)
 {
   if(args.size() != 1)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
   return p->state.pc;
@@ -175,7 +179,7 @@ void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string
 reg_t sim_t::get_reg(const std::vector<std::string>& args)
 {
   if(args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
 
@@ -192,22 +196,22 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
   }
 
   if (r >= NXPR)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   return p->state.XPR[r];
 }
 
-reg_t sim_t::get_freg(const std::vector<std::string>& args)
+freg_t sim_t::get_freg(const std::vector<std::string>& args)
 {
   if(args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
   int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
   if (r == NFPR)
     r = atoi(args[1].c_str());
   if (r >= NFPR)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   return p->state.FPR[r];
 }
@@ -229,29 +233,35 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin
 
 union fpr
 {
-  reg_t r;
+  freg_t r;
   float s;
   double d;
 };
 
+void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
+{
+  freg_t r = get_freg(args);
+  fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
+}
+
 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
   f.r = get_freg(args);
-  fprintf(stderr, "%g\n",f.s);
+  fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN);
 }
 
 void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
   f.r = get_freg(args);
-  fprintf(stderr, "%g\n",f.d);
+  fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN);
 }
 
 reg_t sim_t::get_mem(const std::vector<std::string>& args)
 {
   if(args.size() != 1 && args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   std::string addr_str = args[0];
   mmu_t* mmu = debug_mmu;
@@ -293,7 +303,7 @@ void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::strin
 void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
 {
   if(args.size() != 1)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   reg_t addr = strtol(args[0].c_str(),NULL,16);