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Add debug module authentication.
[riscv-isa-sim.git]
/
riscv
/
jtag_dtm.cc
diff --git
a/riscv/jtag_dtm.cc
b/riscv/jtag_dtm.cc
index 3a0e8d254096903e94ba0f1d828e6cf76d54dbbe..365528a49a7566919c7b0742151f3fab846b5435 100644
(file)
--- a/
riscv/jtag_dtm.cc
+++ b/
riscv/jtag_dtm.cc
@@
-14,7
+14,8
@@
enum {
IR_IDCODE=1,
IR_DTMCONTROL=0x10,
enum {
IR_IDCODE=1,
IR_DTMCONTROL=0x10,
- IR_DBUS=0x11
+ IR_DBUS=0x11,
+ IR_RESET=0x1c
};
#define DTMCONTROL_VERSION 0xf
};
#define DTMCONTROL_VERSION 0xf
@@
-104,8
+105,11
@@
void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
case SHIFT_IR:
_tdo = ir & 1;
break;
case SHIFT_IR:
_tdo = ir & 1;
break;
- case UPDATE_IR:
- break;
+ //case UPDATE_IR:
+ //if (ir == IR_RESET) {
+ // Make a reset happen
+ //}
+ //break;
default:
break;
}
default:
break;
}