enum {
IR_IDCODE=1,
IR_DTMCONTROL=0x10,
- IR_DBUS=0x11
+ IR_DBUS=0x11,
+ IR_RESET=0x1c
};
#define DTMCONTROL_VERSION 0xf
#define DMI_OP_NOP 0
#define DMI_OP_READ 1
-#define DMI_OP_READ_WRITE 2
-#define DMI_OP_RESERVED 3
+#define DMI_OP_WRITE 2
+#define DMI_OP_RESERVED 3
jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
dm(dm),
_tck(false), _tms(false), _tdi(false), _tdo(false),
- dtmcontrol((abits << DTM_DTMCONTROL_ABITS_OFFSET) | 1),
- dmi(DMI_OP_STATUS_FAILED << DTM_DMI_OP_OFFSET),
- state(TEST_LOGIC_RESET)
+ dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1),
+ dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET),
+ _state(TEST_LOGIC_RESET)
{
}
void jtag_dtm_t::reset() {
- state = TEST_LOGIC_RESET;
+ _state = TEST_LOGIC_RESET;
}
void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
if (!_tck && tck) {
// Positive clock edge.
- switch (state) {
+ switch (_state) {
case SHIFT_DR:
dr >>= 1;
dr |= (uint64_t) _tdi << (dr_length-1);
default:
break;
}
- state = next[state][_tms];
- switch (state) {
+ _state = next[_state][_tms];
+ switch (_state) {
case TEST_LOGIC_RESET:
ir = IR_IDCODE;
break;
case SHIFT_IR:
_tdo = ir & 1;
break;
- case UPDATE_IR:
- break;
+ //case UPDATE_IR:
+ //if (ir == IR_RESET) {
+ // Make a reset happen
+ //}
+ //break;
default:
break;
}
}
- /*
D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, "
"dr=0x%lx\n",
- state, _tdi, _tdo, _tms, _tck, ir, dr));
- */
+ _state, _tdi, _tdo, _tms, _tck, ir, dr));
_tck = tck;
_tms = tms;
dmi = dr;
bool success = true;
- if (op == DMI_OP_READ || op == DMI_OP_READ_WRITE) {
+ if (op == DMI_OP_READ) {
uint32_t value;
if (dm->dmi_read(address, &value)) {
dmi = set_field(dmi, DMI_DATA, value);
} else {
success = false;
}
- }
- if (success && op == DMI_OP_READ_WRITE) {
+ } else if (op == DMI_OP_WRITE) {
success = dm->dmi_write(address, data);
}