OpenOCD does a dmi read and gets dummy value back.

[riscv-isa-sim.git] / riscv / jtag_dtm.h

diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h
index e425c8e976cbb51858339b61f779c304e2e06577..2bb45496f76f835950be46cc4c9354a98df0bdd4 100644 (file)
--- a/riscv/jtag_dtm.h
+++ b/riscv/jtag_dtm.h
@@ -3,6 +3,8 @@
 
 #include <stdint.h>
 
+class debug_module_t;
+
 typedef enum {
   TEST_LOGIC_RESET,
   RUN_TEST_IDLE,
@@ -24,58 +26,34 @@ typedef enum {
 
 class jtag_dtm_t
 {
-  static const unsigned idcode_ir = 1;
-  static const unsigned idcode_dr = 0xdeadbeef;
-  static const unsigned dtmcontrol_ir = 0x10;
+  static const unsigned idcode = 0xdeadbeef;
 
   public:
-    jtag_dtm_t() :
-      dtmcontrol(
-          (6 << 4) |        // abits
-          1                 // version
-          ),
-      state(TEST_LOGIC_RESET) {}
-
-    void reset() {
-      state = TEST_LOGIC_RESET;
-    }
+    jtag_dtm_t(debug_module_t *dm);
+    void reset();
 
     void set_pins(bool tck, bool tms, bool tdi);
 
     bool tdo() const { return _tdo; }
 
   private:
+    debug_module_t *dm;
     bool _tck, _tms, _tdi, _tdo;
     uint32_t ir;
     const unsigned ir_length = 5;
     uint64_t dr;
     unsigned dr_length;
 
+    // abits must come before dtmcontrol so it can easily be used in the
+    // constructor.
+    const unsigned abits = 6;
     uint32_t dtmcontrol;
+    uint32_t dbus;
 
     jtag_state_t state;
 
     void capture_dr();
     void update_dr();
-
-    const jtag_state_t next[16][2] = {
-      /* TEST_LOGIC_RESET */    { RUN_TEST_IDLE, TEST_LOGIC_RESET },
-      /* RUN_TEST_IDLE */       { RUN_TEST_IDLE, SELECT_DR_SCAN },
-      /* SELECT_DR_SCAN */      { CAPTURE_DR, SELECT_IR_SCAN },
-      /* CAPTURE_DR */          { SHIFT_DR, EXIT1_DR },
-      /* SHIFT_DR */            { SHIFT_DR, EXIT1_DR },
-      /* EXIT1_DR */            { PAUSE_DR, UPDATE_DR },
-      /* PAUSE_DR */            { PAUSE_DR, EXIT2_DR },
-      /* EXIT2_DR */            { SHIFT_DR, UPDATE_DR },
-      /* UPDATE_DR */           { RUN_TEST_IDLE, SELECT_DR_SCAN },
-      /* SELECT_IR_SCAN */      { CAPTURE_IR, TEST_LOGIC_RESET },
-      /* CAPTURE_IR */          { SHIFT_IR, EXIT1_IR },
-      /* SHIFT_IR */            { SHIFT_IR, EXIT1_IR },
-      /* EXIT1_IR */            { PAUSE_IR, UPDATE_IR },
-      /* PAUSE_IR */            { PAUSE_IR, EXIT2_IR },
-      /* EXIT2_IR */            { SHIFT_IR, UPDATE_IR },
-      /* UPDATE_IR */           { RUN_TEST_IDLE, SELECT_DR_SCAN }
-    };
 };
 
 #endif