Implement resume (untested).

[riscv-isa-sim.git] / riscv / opcodes.h

diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index eb76455c3fbb5cde692a2016588f06ef5ca90f6e..34c089ebb769a1c74d672034941fc0888b8e6243 100644 (file)
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -168,6 +168,9 @@ static uint32_t ebreak(void) { return MATCH_EBREAK; }
 static uint32_t ebreak_c(void) __attribute__ ((unused));
 static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; }
 
+static uint32_t dret(void) __attribute__ ((unused));
+static uint32_t dret(void) { return MATCH_DRET; }
+
 static uint32_t fence_i(void) __attribute__ ((unused));
 static uint32_t fence_i(void)
 {