#include "sim.h"
#include "mmu.h"
#include "disasm.h"
-#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
- : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
+ : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
+ halt_on_reset(halt_on_reset)
{
parse_isa_string(isa);
register_base_instructions();
memset(this, 0, sizeof(*this));
prv = PRV_M;
pc = DEFAULT_RSTVEC;
- mtvec = DEFAULT_MTVEC;
load_reservation = -1;
tselect = 0;
for (unsigned int i = 0; i < num_triggers; i++)
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
+static int xlen_to_uxl(int xlen)
+{
+ if (xlen == 32)
+ return 1;
+ if (xlen == 64)
+ return 2;
+ abort();
+}
+
void processor_t::set_privilege(reg_t prv)
{
assert(prv <= PRV_M);
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc = DEBUG_ROM_START;
+ state.pc = DEBUG_ROM_ENTRY;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
t.get_badaddr());
}
+ if (state.dcsr.cause) {
+ if (t.cause() == CAUSE_BREAKPOINT) {
+ state.pc = DEBUG_ROM_ENTRY;
+ } else {
+ state.pc = DEBUG_ROM_TVEC;
+ }
+ return;
+ }
+
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
(state.prv == PRV_H && state.dcsr.ebreakh) ||
return;
}
- if (state.dcsr.cause) {
- state.pc = DEBUG_ROM_EXCEPTION;
- return;
- }
-
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
- if (bit & ((reg_t)1 << (max_xlen-1)))
+ bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
+ if (interrupt)
deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
// handle the trap in S-mode
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = state.mtvec;
+ reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
+ state.pc = (state.mtvec & ~(reg_t)1) + vector;
state.mepc = epc;
state.mcause = t.cause();
if (t.has_badaddr())
void processor_t::disasm(insn_t insn)
{
+ static uint64_t last_pc = 1, last_bits;
+ static uint64_t executions = 1;
+
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
- id, state.pc, bits, disassembler->disassemble(insn).c_str());
+ if (last_pc != state.pc || last_bits != bits) {
+ if (executions != 1) {
+ fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
+ }
+
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+ id, state.pc, bits, disassembler->disassemble(insn).c_str());
+ last_pc = state.pc;
+ last_bits = bits;
+ executions = 1;
+ } else {
+ executions++;
+ }
}
int processor_t::paddr_bits()
break;
case CSR_MSTATUS: {
if ((val ^ state.mstatus) &
- (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
+ (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
- | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+ | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
| MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
- | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
+ | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
+ (ext ? MSTATUS_XS : 0);
state.mstatus = (state.mstatus & ~mask) | (val & mask);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
- // spike supports the notion of xlen < max_xlen, but current priv spec
- // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
+ // U-XLEN == S-XLEN == M-XLEN
xlen = max_xlen;
break;
}
break;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_PUM;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
case CSR_SIP: {
case CSR_SCAUSE: state.scause = val; break;
case CSR_SBADADDR: state.sbadaddr = val; break;
case CSR_MEPC: state.mepc = val; break;
- case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
+ case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_PUM;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
{
uint32_t v = 0;
v = set_field(v, DCSR_XDEBUGVER, 1);
- v = set_field(v, DCSR_NDRESET, 0);
- v = set_field(v, DCSR_FULLRESET, 0);
- v = set_field(v, DCSR_PRV, state.dcsr.prv);
- v = set_field(v, DCSR_STEP, state.dcsr.step);
- v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
- v = set_field(v, DCSR_STOPCYCLE, 0);
- v = set_field(v, DCSR_STOPTIME, 0);
v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
- v = set_field(v, DCSR_HALT, state.dcsr.halt);
+ v = set_field(v, DCSR_STOPCYCLE, 0);
+ v = set_field(v, DCSR_STOPTIME, 0);
v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+ v = set_field(v, DCSR_STEP, state.dcsr.step);
+ v = set_field(v, DCSR_PRV, state.dcsr.prv);
return v;
}
case CSR_DPC:
case CSR_DSCRATCH:
return state.dscratch;
}
- throw trap_illegal_instruction();
+ throw trap_illegal_instruction(0);
}
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
{
- throw trap_illegal_instruction();
+ throw trap_illegal_instruction(0);
}
insn_func_t processor_t::decode_insn(insn_t insn)
projects / riscv-isa-sim.git / blobdiff