Sv57 and Sv64 are not spec'd yet

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index d44f870574d1ccced46717248c78347f51974a87..0f86f25fabe6fc4058d5a58f44b4b9e6bd600cc8 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -367,7 +367,8 @@ void processor_t::set_csr(int which, reg_t val)
       if (max_xlen == 32)
         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
-                             get_field(val, SPTBR64_MODE) >= SPTBR_MODE_SV39))
+                             get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
+                             get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
       break;
     }