#undef STATE
#define STATE state
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
halt_on_reset(halt_on_reset), last_pc(1), executions(1)
const char* all_subsets = "imafdqc";
max_xlen = 64;
- isa = reg_t(2) << 62;
+ state.misa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
- max_xlen = 32, isa = reg_t(1) << 30, p += 4;
+ max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
}
isa_string = "rv" + std::to_string(max_xlen) + p;
- isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
- isa |= 1L << ('u' - 'a'); // advertise support for user mode
+ state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+ state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
while (*p) {
- isa |= 1L << (*p - 'a');
+ state.misa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
if (supports_extension('Q') && max_xlen < 64)
bad_isa_string(str);
- max_isa = isa;
+ max_isa = state.misa;
}
-void state_t::reset()
+void state_t::reset(reg_t max_isa)
{
memset(this, 0, sizeof(*this));
+ misa = max_isa;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
load_reservation = -1;
void processor_t::reset()
{
- state.reset();
+ state.reset(max_isa);
state.dcsr.halt = halt_on_reset;
halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
+
+ if (sim)
+ sim->proc_reset(id);
}
// Count number of contiguous 0 bits starting from the LSB.
if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
- if (t.has_badaddr())
- fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
- t.get_badaddr());
+ if (t.has_tval())
+ fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id,
+ t.get_tval());
}
if (state.dcsr.cause) {
state.pc = state.stvec;
state.scause = t.cause();
state.sepc = epc;
- state.sbadaddr = t.get_badaddr();
+ state.stval = t.get_tval();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
state.pc = (state.mtvec & ~(reg_t)1) + vector;
state.mepc = epc;
state.mcause = t.cause();
- state.mbadaddr = t.get_badaddr();
+ state.mtval = t.get_tval();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
case CSR_SIE:
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
- case CSR_SPTBR: {
+ case CSR_SATP: {
mmu->flush_tlb();
if (max_xlen == 32)
- state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
- if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
- get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
- get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
- state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
+ state.satp = val & (SATP32_PPN | SATP32_MODE);
+ if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
+ get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
+ get_field(val, SATP64_MODE) == SATP_MODE_SV48))
+ state.satp = val & (SATP64_PPN | SATP64_MODE);
break;
}
- case CSR_SEPC: state.sepc = val; break;
+ case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
- case CSR_SBADADDR: state.sbadaddr = val; break;
- case CSR_MEPC: state.mepc = val; break;
+ case CSR_STVAL: state.stval = val; break;
+ case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
- case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_MTVAL: state.mtval = val; break;
case CSR_MISA: {
if (!(val & (1L << ('F' - 'A'))))
val &= ~(1L << ('D' - 'A'));
mask |= 1L << ('C' - 'A');
mask &= max_isa;
- isa = (val & mask) | (isa & ~mask);
+ state.misa = (val & mask) | (state.misa & ~mask);
break;
}
case CSR_TSELECT:
state.dcsr.halt = get_field(val, DCSR_HALT);
break;
case CSR_DPC:
- state.dpc = val;
+ state.dpc = val & ~(reg_t)1;
break;
case CSR_DSCRATCH:
state.dscratch = val;
case CSR_MINSTRET:
case CSR_MCYCLE:
return state.minstret;
+ case CSR_INSTRETH:
+ case CSR_CYCLEH:
+ if (ctr_ok && xlen == 32)
+ return state.minstret >> 32;
+ break;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
if (xlen == 32)
case CSR_SIP: return state.mip & state.mideleg;
case CSR_SIE: return state.mie & state.mideleg;
case CSR_SEPC: return state.sepc;
- case CSR_SBADADDR: return state.sbadaddr;
+ case CSR_STVAL: return state.stval;
case CSR_STVEC: return state.stvec;
case CSR_SCAUSE:
if (max_xlen > xlen)
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
return state.scause;
- case CSR_SPTBR:
+ case CSR_SATP:
if (get_field(state.mstatus, MSTATUS_TVM))
require_privilege(PRV_M);
- return state.sptbr;
+ return state.satp;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
case CSR_MEPC: return state.mepc;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
- case CSR_MBADADDR: return state.mbadaddr;
- case CSR_MISA: return isa;
+ case CSR_MTVAL: return state.mtval;
+ case CSR_MISA: return state.misa;
case CSR_MARCHID: return 0;
case CSR_MIMPID: return 0;
case CSR_MVENDORID: return 0;
projects / riscv-isa-sim.git / blobdiff