Rename badaddr to tval

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 2d82d917dd8d5b7e4dee2c6848c8e75e5b002211..1b94b1f710e0c69d22e276318331a8e004d6e3cf 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -29,7 +29,7 @@ struct insn_desc_t
 struct commit_log_reg_t
 {
   reg_t addr;
-  reg_t data;
+  freg_t data;
 };
 
 typedef struct
@@ -97,7 +97,7 @@ struct state_t
   reg_t prv;    // TODO: Can this be an enum instead?
   reg_t mstatus;
   reg_t mepc;
-  reg_t mbadaddr;
+  reg_t mtval;
   reg_t mscratch;
   reg_t mtvec;
   reg_t mcause;
@@ -109,10 +109,10 @@ struct state_t
   uint32_t mcounteren;
   uint32_t scounteren;
   reg_t sepc;
-  reg_t sbadaddr;
+  reg_t stval;
   reg_t sscratch;
   reg_t stvec;
-  reg_t sptbr;
+  reg_t satp;
   reg_t scause;
   reg_t dpc;
   reg_t dscratch;
@@ -138,6 +138,8 @@ struct state_t
 #ifdef RISCV_ENABLE_COMMITLOG
   commit_log_reg_t log_reg_write;
   reg_t last_inst_priv;
+  int last_inst_xlen;
+  int last_inst_flen;
 #endif
 };
 
@@ -171,11 +173,18 @@ public:
   reg_t get_csr(int which);
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
+  unsigned get_xlen() { return xlen; }
+  unsigned get_flen() {
+    return supports_extension('Q') ? 128 :
+           supports_extension('D') ? 64 :
+           supports_extension('F') ? 32 : 0;
+  }
   extension_t* get_extension() { return ext; }
   bool supports_extension(unsigned char ext) {
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
   }
+  reg_t legalize_privilege(reg_t);
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
@@ -213,7 +222,6 @@ public:
           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
           (state.prv == PRV_M && !state.mcontrol[i].m) ||
-          (state.prv == PRV_H && !state.mcontrol[i].h) ||
           (state.prv == PRV_S && !state.mcontrol[i].s) ||
           (state.prv == PRV_U && !state.mcontrol[i].u)) {
         continue;