// architectural state of a RISC-V hart
struct state_t
{
- void reset();
+ void reset(reg_t max_isa);
static const int num_triggers = 4;
// control and status registers
reg_t prv; // TODO: Can this be an enum instead?
+ reg_t misa;
reg_t mstatus;
reg_t mepc;
reg_t mtval;
extension_t* get_extension() { return ext; }
bool supports_extension(unsigned char ext) {
if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
- return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
+ return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1);
}
void check_pc_alignment(reg_t pc) {
if (unlikely(pc & 2) && !supports_extension('C'))
uint32_t id;
unsigned max_xlen;
unsigned xlen;
- reg_t isa;
reg_t max_isa;
std::string isa_string;
bool histogram_enabled;