Split ERET into URET, SRET, HRET, MRET

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 1d9b301344b7a190979800879353c1e1eac4753f..2dfe4ed8ac8d88c07919cbf1f0c9d8b6a3007153 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -126,6 +126,8 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       ebreak \
+       ecall \
        fadd_d \
        fadd_s \
        fclass_d \
@@ -202,6 +204,7 @@ riscv_insn_list = \
        lui \
        lw \
        lwu \
+       mret \
        mul \
        mulh \
        mulhsu \
@@ -214,8 +217,6 @@ riscv_insn_list = \
        remuw \
        remw \
        sb \
-       sbreak \
-       scall \
        sc_d \
        sc_w \
        sd \