Refactor remote bitbang code.

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 695803b142ffb0b60b61d3673f379aee7eb8df47..6f12b846a5f30935709e6a3d8a3f9aae1257c250 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -25,6 +25,7 @@ riscv_hdrs = \
        mulhi.h \
        debug_module.h \
        remote_bitbang.h \
+       jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -47,6 +48,7 @@ riscv_srcs = \
        rtc.cc \
        debug_module.cc \
        remote_bitbang.cc \
+       jtag_dtm.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =