work towards rvc 1.8

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 6ddba1d659f0f5c4273e662c143a64180d6c8f81..882f34db7163643e98c41adff43da11aafbe6a21 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -84,8 +84,9 @@ riscv_insn_list = \
        c_addi16sp \
        c_addi4spn \
        c_addi \
-       c_addiw \
        c_addw \
+       c_and \
+       c_andi \
        c_beqz \
        c_bnez \
        c_ebreak \
@@ -103,10 +104,19 @@ riscv_insn_list = \
        c_jr \
        c_li \
        c_lui \
+       c_lbu \
        c_lw \
        c_lwsp \
        c_mv \
+       c_or \
+       c_sll \
        c_slli \
+       c_srai \
+       c_srl \
+       c_srli \
+       c_sub \
+       c_subw \
+       c_xor \
        csrrc \
        csrrci \
        csrrs \