Merge remote-tracking branch 'origin/priv-1.10' into HEAD

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index e9544162f756250c0c5b61493c3709c2a43eec2c..9cd8f4dbef2c08599371c3880e0498d260e19eaf 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -23,8 +23,9 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
-       gdbserver.h \
        debug_module.h \
+       remote_bitbang.h \
+       jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -44,9 +45,12 @@ riscv_srcs = \
        regnames.cc \
        devices.cc \
        rom.cc \
+       rtc.cc \
        clint.cc \
        gdbserver.cc \
        debug_module.cc \
+       remote_bitbang.cc \
+       jtag_dtm.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =