#include "sim.h"
#include "mmu.h"
-#include "gdbserver.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
#include <sstream>
signal(sig, &handle_signal);
}
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
- const std::vector<std::string>& args)
- : htif_t(args), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false), gdbserver(NULL)
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
+ std::vector<std::pair<reg_t, mem_t*>> mems,
+ const std::vector<std::string>& args, std::vector<int> const hartids)
+ : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc),
+ current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
{
signal(SIGINT, &handle_signal);
- // allocate target machine's memory, shrinking it as necessary
- // until the allocation succeeds
- size_t memsz0 = (size_t)mem_mb << 20;
- size_t quantum = 1L << 20;
- if (memsz0 == 0)
- memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
- memsz = memsz0;
- while ((mem = (char*)calloc(1, memsz)) == NULL)
- memsz = (size_t)(memsz*0.9)/quantum*quantum;
+ for (auto& x : mems)
+ bus.add_device(x.first, x.second);
- if (memsz != memsz0)
- fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
- memsz, memsz0);
-
- bus.add_device(DEBUG_START, &debug_module);
+ debug_module.add_device(&bus);
debug_mmu = new mmu_t(this, NULL);
- for (size_t i = 0; i < procs.size(); i++) {
- procs[i] = new processor_t(isa, this, i, halted);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
}
- rtc.reset(new rtc_t(procs));
- make_dtb();
+ clint.reset(new clint_t(procs));
+ bus.add_device(CLINT_BASE, clint.get());
}
sim_t::~sim_t()
for (size_t i = 0; i < procs.size(); i++)
delete procs[i];
delete debug_mmu;
- free(mem);
}
void sim_thread_main(void* arg)
interactive();
else
step(INTERLEAVE);
- if (gdbserver) {
- gdbserver->handle();
+ if (remote_bitbang) {
+ remote_bitbang->tick();
}
}
}
procs[current_proc]->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
- rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+ clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
}
host->switch_to();
void sim_t::make_dtb()
{
- reg_t rtc_addr = EXT_IO_BASE;
- bus.add_device(rtc_addr, rtc.get());
-
- const int align = 0x1000;
- reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
- reg_t cpu_size = align;
-
- uint32_t reset_vec[8] = {
- 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
- 0x00028067, // jump straight to DRAM_BASE
- 0x00000000, // reserved
- 0, // config string pointer
- 0, 0, 0, 0 // trap vector
+ const int reset_vec_size = 8;
+
+ start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
+
+ uint32_t reset_vec[reset_vec_size] = {
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->xlen == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
};
- reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
" riscv,isa = \"" << procs[i]->isa_string << "\";\n"
" mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
" clock-frequency = <" << CPU_HZ << ">;\n"
+ " CPU" << i << "_intc: interrupt-controller {\n"
+ " #interrupt-cells = <1>;\n"
+ " interrupt-controller;\n"
+ " compatible = \"riscv,cpu-intc\";\n"
+ " };\n"
" };\n";
}
- reg_t membs = DRAM_BASE;
- s << std::hex <<
- " };\n"
- " memory@" << DRAM_BASE << " {\n"
+ s << " };\n";
+ for (auto& m : mems) {
+ s << std::hex <<
+ " memory@" << m.first << " {\n"
" device_type = \"memory\";\n"
- " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
- " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
- " };\n"
- " soc {\n"
+ " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
+ " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
+ " };\n";
+ }
+ s << " soc {\n"
" #address-cells = <2>;\n"
" #size-cells = <2>;\n"
- " compatible = \"ucbbar,spike-bare-soc\";\n"
+ " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
" ranges;\n"
- " clint@" << rtc_addr << " {\n"
+ " clint@" << CLINT_BASE << " {\n"
" compatible = \"riscv,clint0\";\n"
" interrupts-extended = <" << std::dec;
for (size_t i = 0; i < procs.size(); i++)
- s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
+ s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
+ reg_t clintbs = CLINT_BASE;
+ reg_t clintsz = CLINT_SIZE;
s << std::hex << ">;\n"
- " reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
- " 0x0 0x10000>;\n"
+ " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
+ " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
" };\n"
" };\n"
+ " htif {\n"
+ " compatible = \"ucb,htif0\";\n"
+ " };\n"
"};\n";
dts = s.str();
std::string dtb = dts_compile(dts);
rom.insert(rom.end(), dtb.begin(), dtb.end());
- rom.resize((rom.size() / align + 1) * align);
+ const int align = 0x1000;
+ rom.resize((rom.size() + align - 1) / align * align);
boot_rom.reset(new rom_device_t(rom));
bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
}
+char* sim_t::addr_to_mem(reg_t addr) {
+ auto desc = bus.find_device(addr);
+ if (auto mem = dynamic_cast<mem_t*>(desc.second))
+ if (addr - desc.first < mem->size())
+ return mem->contents() + (addr - desc.first);
+ return NULL;
+}
+
// htif
+void sim_t::reset()
+{
+ make_dtb();
+}
+
void sim_t::idle()
{
target.switch_to();
projects / riscv-isa-sim.git / blobdiff