+// See LICENSE for license details.
+
#include "sim.h"
-#include "htif.h"
-#include <sys/mman.h>
+#include "mmu.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
+#include <sstream>
#include <climits>
-#include <assert.h>
+#include <cstdlib>
+#include <cassert>
+#include <signal.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <sys/types.h>
-sim_t::sim_t(int _nprocs, htif_t* _htif)
- : htif(_htif),
- procs(_nprocs),
- running(false)
+volatile bool ctrlc_pressed = false;
+static void handle_signal(int sig)
{
- // allocate target machine's memory, shrinking it as necessary
- // until the allocation succeeds
+ if (ctrlc_pressed)
+ exit(-1);
+ ctrlc_pressed = true;
+ signal(sig, &handle_signal);
+}
- size_t memsz0 = sizeof(size_t) == 8 ? 0x100000000ULL : 0x70000000UL;
- size_t quantum = std::max(PGSIZE, (reg_t)sysconf(_SC_PAGESIZE));
- memsz0 = memsz0/quantum*quantum;
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
+ std::vector<std::pair<reg_t, mem_t*>> mems,
+ const std::vector<std::string>& args, std::vector<int> const hartids)
+ : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc),
+ current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
+{
+ signal(SIGINT, &handle_signal);
- memsz = memsz0;
- mem = (char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0);
+ for (auto& x : mems)
+ bus.add_device(x.first, x.second);
- if(mem == MAP_FAILED)
- {
- while(mem == MAP_FAILED && (memsz = memsz*10/11/quantum*quantum))
- mem = (char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0);
- assert(mem != MAP_FAILED);
- fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
- (unsigned long)memsz, (unsigned long)memsz0);
- }
+ debug_module.add_device(&bus);
- mmu = new mmu_t(mem, memsz);
+ debug_mmu = new mmu_t(this, NULL);
- for(size_t i = 0; i < num_cores(); i++)
- procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
+ }
- htif->init(this);
+ clint.reset(new clint_t(procs));
+ bus.add_device(CLINT_BASE, clint.get());
}
sim_t::~sim_t()
{
- for(size_t i = 0; i < num_cores(); i++)
- {
- mmu_t* pmmu = &procs[i]->mmu;
+ for (size_t i = 0; i < procs.size(); i++)
delete procs[i];
- delete pmmu;
+ delete debug_mmu;
+}
+
+void sim_thread_main(void* arg)
+{
+ ((sim_t*)arg)->main();
+}
+
+void sim_t::main()
+{
+ if (!debug && log)
+ set_procs_debug(true);
+
+ while (!done())
+ {
+ if (debug || ctrlc_pressed)
+ interactive();
+ else
+ step(INTERLEAVE);
+ if (remote_bitbang) {
+ remote_bitbang->tick();
+ }
+ }
+}
+
+int sim_t::run()
+{
+ host = context_t::current();
+ target.init(sim_thread_main, this);
+ return htif_t::run();
+}
+
+void sim_t::step(size_t n)
+{
+ for (size_t i = 0, steps = 0; i < n; i += steps)
+ {
+ steps = std::min(n - i, INTERLEAVE - current_step);
+ procs[current_proc]->step(steps);
+
+ current_step += steps;
+ if (current_step == INTERLEAVE)
+ {
+ current_step = 0;
+ procs[current_proc]->yield_load_reservation();
+ if (++current_proc == procs.size()) {
+ current_proc = 0;
+ clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+ }
+
+ host->switch_to();
+ }
}
- delete mmu;
- munmap(mem, memsz);
}
-void sim_t::set_tohost(reg_t val)
+void sim_t::set_debug(bool value)
+{
+ debug = value;
+}
+
+void sim_t::set_log(bool value)
{
- fromhost = 0;
- tohost = val;
+ log = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i]->set_histogram(histogram_enabled);
+ }
}
-reg_t sim_t::get_fromhost()
+void sim_t::set_procs_debug(bool value)
{
- htif->wait_for_fromhost_write();
- return fromhost;
+ for (size_t i=0; i< procs.size(); i++)
+ procs[i]->set_debug(value);
}
-void sim_t::send_ipi(reg_t who)
+bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
{
- if(who < num_cores())
- procs[who]->deliver_ipi();
+ if (addr + len < addr)
+ return false;
+ return bus.load(addr, len, bytes);
}
-void sim_t::run(bool debug)
+bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
{
- htif->wait_for_start();
+ if (addr + len < addr)
+ return false;
+ return bus.store(addr, len, bytes);
+}
- // start core 0
- send_ipi(0);
+static std::string dts_compile(const std::string& dts)
+{
+ // Convert the DTS to DTB
+ int dts_pipe[2];
+ pid_t dts_pid;
- for(running = true; running; )
- {
- if(!debug)
- step_all(100,100,false);
- else
- interactive();
+ if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
+ std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
+ exit(1);
}
+
+ // Child process to output dts
+ if (dts_pid == 0) {
+ close(dts_pipe[0]);
+ int step, len = dts.length();
+ const char *buf = dts.c_str();
+ for (int done = 0; done < len; done += step) {
+ step = write(dts_pipe[1], buf+done, len-done);
+ if (step == -1) {
+ std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+ }
+ close(dts_pipe[1]);
+ exit(0);
+ }
+
+ pid_t dtb_pid;
+ int dtb_pipe[2];
+ if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
+ std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+
+ // Child process to output dtb
+ if (dtb_pid == 0) {
+ dup2(dts_pipe[0], 0);
+ dup2(dtb_pipe[1], 1);
+ close(dts_pipe[0]);
+ close(dts_pipe[1]);
+ close(dtb_pipe[0]);
+ close(dtb_pipe[1]);
+ execl(DTC, DTC, "-O", "dtb", 0);
+ std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
+ exit(1);
+ }
+
+ close(dts_pipe[1]);
+ close(dts_pipe[0]);
+ close(dtb_pipe[1]);
+
+ // Read-out dtb
+ std::stringstream dtb;
+
+ int got;
+ char buf[4096];
+ while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
+ dtb.write(buf, got);
+ }
+ if (got == -1) {
+ std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+ close(dtb_pipe[0]);
+
+ // Reap children
+ int status;
+ waitpid(dts_pid, &status, 0);
+ if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
+ std::cerr << "Child dts process failed" << std::endl;
+ exit(1);
+ }
+ waitpid(dtb_pid, &status, 0);
+ if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
+ std::cerr << "Child dtb process failed" << std::endl;
+ exit(1);
+ }
+
+ return dtb.str();
+}
+
+void sim_t::make_dtb()
+{
+ const int reset_vec_size = 8;
+
+ start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
+
+ uint32_t reset_vec[reset_vec_size] = {
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->xlen == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
+ };
+
+ std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
+
+ std::stringstream s;
+ s << std::dec <<
+ "/dts-v1/;\n"
+ "\n"
+ "/ {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-dev\";\n"
+ " model = \"ucbbar,spike-bare\";\n"
+ " cpus {\n"
+ " #address-cells = <1>;\n"
+ " #size-cells = <0>;\n"
+ " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
+ for (size_t i = 0; i < procs.size(); i++) {
+ s << " CPU" << i << ": cpu@" << i << " {\n"
+ " device_type = \"cpu\";\n"
+ " reg = <" << i << ">;\n"
+ " status = \"okay\";\n"
+ " compatible = \"riscv\";\n"
+ " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
+ " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
+ " clock-frequency = <" << CPU_HZ << ">;\n"
+ " CPU" << i << "_intc: interrupt-controller {\n"
+ " #interrupt-cells = <1>;\n"
+ " interrupt-controller;\n"
+ " compatible = \"riscv,cpu-intc\";\n"
+ " };\n"
+ " };\n";
+ }
+ s << " };\n";
+ for (auto& m : mems) {
+ s << std::hex <<
+ " memory@" << m.first << " {\n"
+ " device_type = \"memory\";\n"
+ " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
+ " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
+ " };\n";
+ }
+ s << " soc {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
+ " ranges;\n"
+ " clint@" << CLINT_BASE << " {\n"
+ " compatible = \"riscv,clint0\";\n"
+ " interrupts-extended = <" << std::dec;
+ for (size_t i = 0; i < procs.size(); i++)
+ s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
+ reg_t clintbs = CLINT_BASE;
+ reg_t clintsz = CLINT_SIZE;
+ s << std::hex << ">;\n"
+ " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
+ " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
+ " };\n"
+ " };\n"
+ " htif {\n"
+ " compatible = \"ucb,htif0\";\n"
+ " };\n"
+ "};\n";
+
+ dts = s.str();
+ std::string dtb = dts_compile(dts);
+
+ rom.insert(rom.end(), dtb.begin(), dtb.end());
+ const int align = 0x1000;
+ rom.resize((rom.size() + align - 1) / align * align);
+
+ boot_rom.reset(new rom_device_t(rom));
+ bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
+}
+
+char* sim_t::addr_to_mem(reg_t addr) {
+ auto desc = bus.find_device(addr);
+ if (auto mem = dynamic_cast<mem_t*>(desc.second))
+ if (addr - desc.first < mem->size())
+ return mem->contents() + (addr - desc.first);
+ return NULL;
+}
+
+// htif
+
+void sim_t::reset()
+{
+ make_dtb();
+}
+
+void sim_t::idle()
+{
+ target.switch_to();
+}
+
+void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
+{
+ assert(len == 8);
+ auto data = debug_mmu->load_uint64(taddr);
+ memcpy(dst, &data, sizeof data);
}
-void sim_t::step_all(size_t n, size_t interleave, bool noisy)
+void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
{
- for(size_t j = 0; j < n; j+=interleave)
- for(int i = 0; i < (int)num_cores(); i++)
- procs[i]->step(interleave,noisy);
+ assert(len == 8);
+ uint64_t data;
+ memcpy(&data, src, sizeof data);
+ debug_mmu->store_uint64(taddr, data);
}
projects / riscv-isa-sim.git / blobdiff