+// See LICENSE for license details.
+
#ifndef _RISCV_SIM_H
#define _RISCV_SIM_H
+#include "processor.h"
+#include "devices.h"
+#include "debug_module.h"
+#include "simif.h"
+#include <fesvr/htif.h>
+#include <fesvr/context.h>
#include <vector>
#include <string>
-#include "processor.h"
-#include "mmu.h"
+#include <memory>
-class htif_t;
+class mmu_t;
+class remote_bitbang_t;
// this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t
+class sim_t : public htif_t, public simif_t
{
public:
- sim_t(int _nprocs, htif_t* _htif);
+ sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc,
+ std::vector<std::pair<reg_t, mem_t*>> mems,
+ const std::vector<std::string>& args, const std::vector<int> hartids,
+ unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
~sim_t();
// run the simulation to completion
- void run(bool debug);
-
- // communicate with the host machine
- void set_tohost(reg_t val);
- reg_t get_tohost();
- reg_t get_fromhost();
-
- // deliver an IPI to a specific processor
- void send_ipi(reg_t who);
-
- // returns the number of processors in this simulator
- size_t num_cores() { return procs.size(); }
+ int run();
+ void set_debug(bool value);
+ void set_log(bool value);
+ void set_histogram(bool value);
+ void set_procs_debug(bool value);
+ void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+ this->remote_bitbang = remote_bitbang;
+ }
+ const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); }
+ processor_t* get_core(size_t i) { return procs.at(i); }
+ unsigned nprocs() const { return procs.size(); }
+
+ // Callback for processors to let the simulation know they were reset.
+ void proc_reset(unsigned id);
private:
- htif_t* htif;
-
- // global registers for communication with host machine
- reg_t tohost;
- reg_t fromhost;
-
- // main memory, shared between processors
- char* mem;
- size_t memsz; // memory size in bytes
- mmu_t* mmu; // debug port into main memory
-
- // processors
+ std::vector<std::pair<reg_t, mem_t*>> mems;
+ mmu_t* debug_mmu; // debug port into main memory
std::vector<processor_t*> procs;
-
- // terminate the simulation loop after the current iteration
- void stop() { running = false; }
- bool running;
-
- // run each processor for n instructions; interleave instructions are
- // run on a processor before moving on to the next processor.
- // interleave must divide n.
- // if noisy, print out the instructions as they execute.
- void step_all(size_t n, size_t interleave, bool noisy);
+ reg_t start_pc;
+ std::string dts;
+ std::unique_ptr<rom_device_t> boot_rom;
+ std::unique_ptr<clint_t> clint;
+ bus_t bus;
+
+ processor_t* get_core(const std::string& i);
+ void step(size_t n); // step through simulation
+ static const size_t INTERLEAVE = 5000;
+ static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
+ static const size_t CPU_HZ = 1000000000; // 1GHz CPU
+ size_t current_step;
+ size_t current_proc;
+ bool debug;
+ bool log;
+ bool histogram_enabled; // provide a histogram of PCs
+ remote_bitbang_t* remote_bitbang;
+
+ // memory-mapped I/O routines
+ char* addr_to_mem(reg_t addr);
+ bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
+ bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
+ void make_dtb();
// presents a prompt for introspection into the simulation
void interactive();
// functions that help implement interactive()
+ void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
- void interactive_run_proc(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
- void interactive_run_proc_noisy(const std::string& cmd, const std::vector<std::string>& args);
- void interactive_run_proc_silent(const std::string& cmd, const std::vector<std::string>& args);
void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
+ void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
+ void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
reg_t get_reg(const std::vector<std::string>& args);
- reg_t get_freg(const std::vector<std::string>& args);
+ freg_t get_freg(const std::vector<std::string>& args);
reg_t get_mem(const std::vector<std::string>& args);
reg_t get_pc(const std::vector<std::string>& args);
- reg_t get_tohost(const std::vector<std::string>& args);
- friend class htif_t;
+ friend class processor_t;
+ friend class mmu_t;
+ friend class debug_module_t;
+
+ // htif
+ friend void sim_thread_main(void*);
+ void main();
+
+ context_t* host;
+ context_t target;
+ void reset();
+ void idle();
+ void read_chunk(addr_t taddr, size_t len, void* dst);
+ void write_chunk(addr_t taddr, size_t len, const void* src);
+ size_t chunk_align() { return 8; }
+ size_t chunk_max_size() { return 8; }
+
+public:
+ // Initialize this after procs, because in debug_module_t::reset() we
+ // enumerate processors, which segfaults if procs hasn't been initialized
+ // yet.
+ debug_module_t debug_module;
};
+extern volatile bool ctrlc_pressed;
+
#endif
projects / riscv-isa-sim.git / blobdiff