reorganise twin-predication

[riscv-isa-sim.git] / riscv / sv_decode.h

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index aabbe79faaf070d5277fa04179615cb2bb1ebba1..7bffe1b47934c6f611a72f5053988cf27ff8d1a0 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -21,48 +21,32 @@ class sv_insn_t: public insn_t
 {
 public:
   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
-            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) :
+            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
+            int &o_rd, int &o_rs1, int &o_rs2, int &o_rs3) :
             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
-            cached_rd(0xff), cached_rs1(0xff),
-            cached_rs2(0xff), cached_rs3(0xff),
-            offs_rd(0), offs_rs(0),
-            new_offs_rd(0), new_offs_rs(0),
+            offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
   uint64_t rd () { return predicated(_rd (), offs_rd, prd); }
-  uint64_t rs1() { return predicated(_rs1(), offs_rs, prs1); }
-  uint64_t rs2() { return predicated(_rs2(), offs_rs, prs2); }
-  uint64_t rs3() { return predicated(_rs3(), offs_rs, prs3); }
-  uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs, prs1); }
-  uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs, prs1); }
-  uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs, prs2); }
-  uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs, prs2); }
+  uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); }
+  uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); }
+  uint64_t rs3() { return predicated(_rs3(), offs_rs3, prs3); }
+  uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs1, prs1); }
+  uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); }
+  uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); }
+  uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); }
 
-  uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD ,
-                                  offs_rd , cached_rd, new_offs_rd); }
-  uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1,
-                                  offs_rs, cached_rs1, new_offs_rs); }
-  uint64_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2,
-                                  offs_rs, cached_rs2, new_offs_rs); }
-  uint64_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3,
-                                  offs_rs, cached_rs3, new_offs_rs); }
+  uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD , offs_rd); }
+  uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1, offs_rs1); }
+  uint64_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2, offs_rs2); }
+  uint64_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3, offs_rs3); }
   uint64_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(), fimap & REG_RVC_RS1,
-                                       offs_rs, cached_rs1, new_offs_rs); }
+                                       offs_rs1); }
   uint64_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(), fimap & REG_RVC_RS1S,
-                                       offs_rs, cached_rs1, new_offs_rs); }
+                                       offs_rs1); }
   uint64_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(), fimap & REG_RVC_RS2,
-                                       offs_rs, cached_rs2, new_offs_rs); }
+                                       offs_rs2); }
   uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
-                                       offs_rs, cached_rs2, new_offs_rs); }
-
-  void reset_caches(void)
-  {
-    cached_rd = 0xff;
-    cached_rs1 = 0xff;
-    cached_rs2 = 0xff;
-    cached_rs3 = 0xff;
-    offs_rd = new_offs_rd;
-    offs_rs = new_offs_rs;
-  }
+                                       offs_rs2); }
 
   bool sv_check_reg(bool intreg, uint64_t reg);
   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
@@ -72,23 +56,14 @@ public:
   void reset_vloop_check(void) { vloop_continue = false; }
   bool stop_vloop(void);
 
-  int rd_offs(void) { return offs_rd; }
-  int rs_offs(void) { return offs_rs; }
-  int rd_offs_inc(void) { offs_rd += 1; return offs_rd; }
-  int rs_offs_inc(void) { offs_rs += 1; return offs_rs; }
-
   processor_t *p;
 private:
   bool vloop_continue;
   unsigned int fimap;
-  uint64_t cached_rd;
-  uint64_t cached_rs1;
-  uint64_t cached_rs2;
-  uint64_t cached_rs3;
-  int offs_rd;
-  int offs_rs;
-  int new_offs_rd;
-  int new_offs_rs;
+  int &offs_rd;
+  int &offs_rs1;
+  int &offs_rs2;
+  int &offs_rs3;
   uint64_t &prd;
   uint64_t &prs1;
   uint64_t &prs2;
@@ -96,26 +71,18 @@ private:
 
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
-  uint64_t remap(uint64_t reg, bool isint, int &offs, int &newoffs);
+  uint64_t remap(uint64_t reg, bool isint, int &offs);
 
   // cached version of remap: if remap is called multiple times
   // by an emulated instruction it would increment the loop offset
   // before it's supposed to.
-  uint64_t _remap(uint64_t reg, bool isint, int &offs,
-                  uint64_t &cached, int &newoffs)
+  uint64_t _remap(uint64_t reg, bool isint, int &offs)
   {
-    if (cached == 0xff)
-    {
-        cached = remap(reg, isint, offs, newoffs);
-    }
-    else
+    if (sv_check_reg(isint, reg))
     {
-        if (sv_check_reg(isint, reg))
-        {
-            vloop_continue = true;
-        }
+        vloop_continue = true;
     }
-    return cached;
+    return remap(reg, isint, offs);
   }
 
   uint64_t predicated(uint64_t reg, int offs, uint64_t pred);