Move towards RVC v1.8

[riscv-isa-sim.git] / spike_main / disasm.cc

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index e6336d0bd3c3d57a8bcabd032463ee97720a3281..e32bad5897edc000474d2938349791da99327cad 100644 (file)
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -144,12 +144,6 @@ struct : public arg_t {
   }
 } rvc_rs2s;
 
-struct : public arg_t {
-  std::string to_string(insn_t insn) const {
-    return xpr_name[insn.rvc_rds()];
-  }
-} rvc_rds;
-
 struct : public arg_t {
   std::string to_string(insn_t insn) const {
     return xpr_name[X_SP];
@@ -514,13 +508,13 @@ disassembler_t::disassembler_t()
   DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs1});
   DISASM_INSN("addw", c_addw, 0, {&xrd, &xrd, &rvc_rs1});
   DISASM_INSN("lw", c_lwsp, 0, {&xrd, &rvc_lwsp_address});
-  DISASM_INSN("ld", c_ldsp, 0, {&xrd, &rvc_ldsp_address});
+  DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address});
   DISASM_INSN("sw", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address});
-  DISASM_INSN("sd", c_sdsp, 0, {&rvc_rs2, &rvc_sdsp_address});
+  DISASM_INSN("fsw", c_fswsp, 0, {&rvc_rs2, &rvc_swsp_address});
   DISASM_INSN("lw", c_lw, 0, {&rvc_rs2s, &rvc_lw_address});
-  DISASM_INSN("ld", c_ld, 0, {&rvc_rs2s, &rvc_ld_address});
+  DISASM_INSN("flw", c_flw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("sw", c_sw, 0, {&rvc_rs2s, &rvc_lw_address});
-  DISASM_INSN("sd", c_sd, 0, {&rvc_rs2s, &rvc_ld_address});
+  DISASM_INSN("fsw", c_fsw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("beqz", c_beqz, 0, {&rvc_rs1s, &rvc_branch_target});
   DISASM_INSN("bnez", c_bnez, 0, {&rvc_rs1s, &rvc_branch_target});
   DISASM_INSN("j", c_j, 0, {&rvc_jump_target});