projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 992205c) | patch
Set badvaddr on instruction page faults
authorAndrew Waterman <waterman@cs.berkeley.edu>
Fri, 5 Dec 2014 07:08:01 +0000 (23:08 -0800)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Fri, 5 Dec 2014 07:08:01 +0000 (23:08 -0800)
commitcec752d09191e96a51f5c21ed8d51e1218f804ff
tree80a611deb7791f4dbe2ac8d726f761aa13cd2374tree
parent992205c27048709b85c2655bc5ce797dd2246f75commit | diff
Set badvaddr on instruction page faults

This supports distinguishing the EPC (the address of the first byte of the
faulting instruction) from the address of the page fault (potentially some
bytes later).
riscv/decode.h diff | blob | history
riscv/mmu.cc diff | blob | history
riscv/trap.h diff | blob | history
Simple-V augmented version of spike