Set badvaddr on instruction page faults

This supports distinguishing the EPC (the address of the first byte of the
faulting instruction) from the address of the page fault (potentially some
bytes later).

diff --git a/riscv/decode.h b/riscv/decode.h
index 989051454661f341984b60729a7f3b1983a93728..543080ddf4ca2c1a551d41b3f78f50afe1ff24ee 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -155,7 +155,7 @@ private:
 
 #define set_pc(x) \
   do { if ((x) & 3 /* For now... */) \
-         throw trap_instruction_address_misaligned(); \
+         throw trap_instruction_address_misaligned(x); \
        npc = sext_xprlen(x); \
      } while(0)
 

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 4675f75f61734963054980c6c2c8efa448ff289b..92cb6dee955003559f9c705c6b5633661c895400 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -45,8 +45,7 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
   if(unlikely((pte_perm & perm) != perm))
   {
     if (fetch)
-      throw trap_instruction_access_fault();
-
+      throw trap_instruction_access_fault(addr);
     if (store)
       throw trap_store_access_fault(addr);
     throw trap_load_access_fault(addr);

diff --git a/riscv/trap.h b/riscv/trap.h
index b79594885fdc06e0396c9e72763c8cf14308c25d..53df4f4033f0fc4e9d2efc17a404aea6e2760c12 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -42,8 +42,8 @@ class mem_trap_t : public trap_t
   const char* name() { return "trap_"#x; } \
 };
 
-DECLARE_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
-DECLARE_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
 DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
 DECLARE_TRAP(CAUSE_PRIVILEGED_INSTRUCTION, privileged_instruction)
 DECLARE_TRAP(CAUSE_FP_DISABLED, fp_disabled)