+ reg_t membs = DRAM_BASE;
+ s << std::hex <<
+ " };\n"
+ " memory@" << DRAM_BASE << " {\n"
+ " device_type = \"memory\";\n"
+ " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
+ " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
+ " };\n"
+ " soc {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-soc\";\n"
+ " ranges;\n"
+ " clint@" << rtc_addr << " {\n"
+ " compatible = \"riscv,clint0\";\n"
+ " interrupts-extended = <" << std::dec;
+ for (size_t i = 0; i < procs.size(); i++)
+ s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
+ s << std::hex << ">;\n"
+ " reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
+ " 0x0 0x10000>;\n"
+ " };\n"
+ " };\n"
+ "};\n";