Set U bit in misa register

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8c89e3f6aedd2923077bb2b3c181f18704771f2b..8c267f4964456e64ad5e4a9b944a8f81219e2aa7 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -84,6 +84,7 @@ void processor_t::parse_isa_string(const char* str)
 
   isa_string = "rv" + std::to_string(max_xlen) + p;
   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+  isa |= 1L << ('u' - 'a'); // advertise support for user mode
 
   while (*p) {
     isa |= 1L << (*p - 'a');