For misaligned fetch, set mepc = addr of branch/jump

diff --git a/riscv/decode.h b/riscv/decode.h
index 2fdb042f5074b18090664aad86ff295699ad26e5..4ad45490b95447074bc8082e4c37086bd8f3ee4c 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -153,7 +153,11 @@ private:
 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
-#define set_pc(x) (npc = sext_xlen(x))
+#define set_pc(x) \
+  do { if ((x) & 3 /* For now... */) \
+         throw trap_instruction_address_misaligned(x); \
+       npc = sext_xlen(x); \
+     } while(0)
 
 #define validate_csr(which, write) ({ \
   unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \