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Add some missing RVC instructions to disassembler
author
Andrew Waterman
<andrew@sifive.com>
Wed, 3 Jan 2018 21:06:21 +0000
(13:06 -0800)
committer
Andrew Waterman
<andrew@sifive.com>
Wed, 3 Jan 2018 21:06:21 +0000
(13:06 -0800)
spike_main/disasm.cc
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diff --git
a/spike_main/disasm.cc
b/spike_main/disasm.cc
index 49f4de2ed802256e14c4d97e446e16a8544846a6..982064d5641b3ddc570a75acf7b9186e27a95584 100644
(file)
--- a/
spike_main/disasm.cc
+++ b/
spike_main/disasm.cc
@@
-545,6
+545,9
@@
disassembler_t::disassembler_t(int xlen)
DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm});
DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm});
DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
+ DISASM_INSN("srli", c_srli, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt});
+ DISASM_INSN("srai", c_srai, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt});
+ DISASM_INSN("andi", c_andi, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_imm});
DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2});
DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2});
DISASM_INSN("addw", c_addw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2});
DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2});
DISASM_INSN("addw", c_addw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});