projects
/
riscv-isa-sim.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
3b1e9ab
)
Don't permit delegation of interrupts that M-mode should handle
author
Andrew Waterman
<andrew@sifive.com>
Thu, 2 Nov 2017 01:57:02 +0000
(18:57 -0700)
committer
Andrew Waterman
<andrew@sifive.com>
Thu, 2 Nov 2017 01:57:02 +0000
(18:57 -0700)
riscv/processor.cc
patch
|
blob
|
history
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index ae021657b680819b89b766eca566582731ebf29d..203394b679de0e3749d1ca7e96f943e3b07a26a6 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-360,10
+360,9
@@
void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT
+ | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT
+ | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT;
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}