On EBREAK, set badaddr to pc
authorAndrew Waterman <andrew@sifive.com>
Tue, 28 Mar 2017 04:21:57 +0000 (21:21 -0700)
committerAndrew Waterman <andrew@sifive.com>
Tue, 28 Mar 2017 04:21:57 +0000 (21:21 -0700)
riscv/insns/c_ebreak.h
riscv/insns/ebreak.h
riscv/trap.h

index a17200fa4dec4a6b3fd2d7fb4e2be078fd133d71..128b86b22c55beefbd0eb8ca43f3c3a3708676b7 100644 (file)
@@ -1,2 +1,2 @@
 require_extension('C');
-throw trap_breakpoint();
+throw trap_breakpoint(pc);
index c22776c80278f7cd4dab81cba331f52c75fa08b8..736cebef4b63e8a98674b836aebe06a341e972c9 100644 (file)
@@ -1 +1 @@
-throw trap_breakpoint();
+throw trap_breakpoint(pc);
index a289a6842af5aff0c5782e175a7f6331eac33605..20313e99c75c5a0f9b42e9f44468378d912d8fde 100644 (file)
@@ -47,7 +47,7 @@ class mem_trap_t : public trap_t
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
 DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)