- fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
- fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 4096]\n");
- fprintf(stderr, " -d Interactive debug mode\n");
- fprintf(stderr, " -g Track histogram of PCs\n");
- fprintf(stderr, " -l Generate a log of execution\n");
- fprintf(stderr, " -h Print this help message\n");
- fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
- fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
- fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
- fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
- fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
- fprintf(stderr, " --extlib=<name> Shared library to load\n");
+ fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
+ fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 4096]\n");
+ fprintf(stderr, " -d Interactive debug mode\n");
+ fprintf(stderr, " -g Track histogram of PCs\n");
+ fprintf(stderr, " -l Generate a log of execution\n");
+ fprintf(stderr, " -h Print this help message\n");
+ fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
+ fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
+ fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
+ fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
+ fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
+ fprintf(stderr, " --extlib=<name> Shared library to load\n");
+ fprintf(stderr, " --dump-config-string Print platform configuration string and exit\n");