now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.
val = badvaddr;
break;
case 3:
- val = ebase;
+ val = evec;
break;
case 4:
val = count;
case 5:
val = compare;
break;
+ case 6:
+ val = cause;
+ break;
case 8:
val = MEMSIZE >> 12;
epc = RS1;
break;
case 3:
- ebase = RS1 & ~0xFFF;
+ evec = RS1;
break;
case 4:
count = RS1;
{
if(addr & (size-1))
{
+ badvaddr = addr;
if(fetch)
throw trap_instruction_address_misaligned;
- badvaddr = addr;
throw trap_data_address_misaligned;
}
}
{
if(addr >= memsz || addr + size > memsz)
{
+ badvaddr = addr;
if(fetch)
throw trap_instruction_access_fault;
- badvaddr = addr;
throw store ? trap_store_access_fault : trap_load_access_fault;
}
}
memset(R,0,sizeof(R));
memset(FR,0,sizeof(FR));
pc = 0;
- ebase = 0;
+ evec = 0;
epc = 0;
badvaddr = 0;
+ cause = 0;
tid = 0;
pcr_k0 = 0;
pcr_k1 = 0;
id, trap_name(t), (unsigned long long)pc);
set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
+ cause = t;
epc = pc;
- pc = ebase + t*128;
+ pc = evec;
badvaddr = mmu.get_badvaddr();
}
reg_t pc;
reg_t epc;
reg_t badvaddr;
- reg_t ebase;
+ reg_t cause;
+ reg_t evec;
reg_t tohost;
reg_t fromhost;
reg_t pcr_k0;